In reply to dave_59:
In reply to megamind:
When dealing with container classes in SystemVerilog, you need to understand the differences between “shallow” and “deep” access. When it comes to things like copying, comparing, and printing a hierarchy of contained classes, you must provide the necessary methods that traverse the hierarchy. That is what’s call a “deep” dive into the class. Otherwise, all you see is the top-level container, or “shallow” view of the class.
class Container;
Register regs[];
string m_name;
function new (string name);
m_name = name;
regs = new[3];
regs[0] = new("first");
regs[1] = new("second");
regs[2] = new("third");
endfunction
function void print();
$display(m_name);
foreach(regs[i]) regs[i].print();
endfunction
endclass
module tb;
Container c;
initial begin
c = new("MainContainer");
$display ("-------- Initial Values --------");
c.print();
end
endmodule
Thank you Dave, on the systemverilog level it’s pretty clear now (at least seems to be) what needs to happen. On the UVM side – I was hoping, that if I have uvm_field_array_object(array_of_objects, UVM_ALL_ON) macro inside of the uvm_object_utils_begin/end construct, then this extension of the standard methods (like print, etc.) to cover the array_of_objects would happen automagically. Is it the case or not?