Regarding assertion

UVM
,
7

In reply to chr_sue:

class fifo_driver extends uvm_driver # (amd_apb_transaction);

typedef virtual fifo_interface fifo_vif;
fifo_vif vif;
static int count = 0;
extern function new(string name = “fifo_driver”, uvm_component parent = null);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual protected task wclk_gen();
extern virtual protected task rclk_gen();
extern virtual protected task get_and_drive();
extern virtual protected task write(input bit [3:0] data);
extern virtual protected task read(output logic [3:0] data);
endclass: fifo_driver

task fifo_driver::run_phase(uvm_phase phase);
super.run_phase(phase);
fork
this.get_and_drive();
this.wclk_gen();
this.rclk_gen();
join
endtask: run_phase
// ---------------------- clock generation ---------------------- //
task fifo_driver::wclk_gen();

bit clk;
this.pclk_en = 1;
this.vif.WCLK = 0;

forever begin
if (this.pclk_en == 1)begin
#(PCLK_PERIOD/2); clk = ~clk; this.vif.WCLK = clk; end else begin uvm_info($sformatf(“%s:CLK_GEN”,get_name()), “STOPPING WPCLK”, UVM_LOW)
break;
end
end

endtask: wclk_gen

// ---------------------- DFI clock generation ---------------------- //
task fifo_driver::rclk_gen();

bit dficlk=0;
this.dficlk_en = 1;
this.vif.RCLK = 0;

forever begin
if (this.dficlk_en == 1)begin
#(DFI_CLK_PERIOD/2); dficlk = ~dficlk; this.vif.RCLK = dficlk; end else begin uvm_info($sformatf(“%s:CLK_GEN”,get_name()), “STOPPING DFICLK”, UVM_LOW)
break;
end
end

endtask: rclk_gen

// ---------------------- get_and_drive ---------------------- //
task fifo_driver::get_and_drive();

`uvm_info($sformatf(“%s:get_and_drive”,get_name()), “STARTING get_and_drive”, UVM_LOW)

forever begin
fifo_transaction tr;
seq_item_port.get_next_item(tr);

  fork
  case (tr.kind)
    fifo_transaction::read        : this.read( tr.rdata);  
    fifo_transaction::write       : this.write(tr.wdata);
  endcase
join_any
disable fork;
seq_item_port.item_done();

end //forever begin
`uvm_info($sformatf(“%s:get_and_drive”,get_name()), “STOPPING get_and_drive”, UVM_LOW)
endtask: get_and_drive

// ---------------------- Read operation ---------------------- //
static task fifo_driver::read(output logic [3:0] data);

this.vif.RE = 1’b1;
@(posedge this.vif.RCLK);
if (count != 1’b0) begin
data = this.vif.PRDATA;
count = count - 1;
$display(“read count %d time %t”,count,$time);

end
else
begin
$display(“count in else part %d time %t”,count,$time);
end
this.vif.RE = 1’b0;
endtask: read
//
//// ---------------------- Write operation ---------------------- //
static task fifo_driver::write(input bit [3:0] data);

this.vif.WE = 1’b1;
@(posedge this.vif.WCLK);
if (count <= `FIFO_SIZE) begin
this.vif.PWDATA = data;
count = count + 1;
$display(“write count %d time %t”,count,$time);
//this.vif.fifo_full = 1’b0;
end
else
begin
$display(“count in else part %d”,count);
end
this.vif.WE = 1’b0;
endtask: write