In reply to chr_sue:
In reply to chr_sue:
And here is the complete code, compiling in Questa without errors:
import uvm_pkg::*;
`include "uvm_macros.svh"
typedef class fifo_driver;
interface fifo_interface (input logic WCLK, input logic RCLK);
logic PSEL, PENABLE, PWRITE;
logic [15:0] PADDR;
logic [31:0] PWDATA;
logic [31:0] PRDATA;
bit full;
fifo_driver drv_count;
property check_for_fifofull;
@(posedge WCLK) (drv_count.count == 20) |=> full ;
endproperty
property check_for_fifoempty;
@(posedge RCLK) (drv_count.count == 0 ) |=> !full ;
endproperty
check_full : assert property (check_for_fifofull)
else
`uvm_error("CHECK FOR FIFO FULL FAILED","fifo")
check_empty : assert property (check_for_fifoempty)
else
`uvm_error("CHECK FOR FIFO EMPTY FAILED","fifo")
endinterface
class fifo_transaction extends uvm_object;
int rdata;
int wdata;
enum {read, write} kind;
function new(string name = "");
super.new(name);
endfunction
endclass
class amd_apb_transaction extends uvm_object;
function new(string name = "");
super.new(name);
endfunction
endclass
class fifo_driver extends uvm_driver # (amd_apb_transaction);
typedef virtual fifo_interface fifo_vif;
fifo_vif vif;
static int count = 0;
extern function new(string name = "fifo_driver", uvm_component parent = null);
//extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual protected task wclk_gen();
extern virtual protected task rclk_gen();
extern virtual protected task get_and_drive();
extern virtual protected task write(input bit [3:0] data);
extern virtual protected task read(output logic [3:0] data);
endclass: fifo_driver
task fifo_driver::run_phase(uvm_phase phase);
super.run_phase(phase);
fork
this.get_and_drive();
this.wclk_gen();
this.rclk_gen();
join
endtask: run_phase
// ---------------------- clock generation ---------------------- //
task fifo_driver::wclk_gen();
bit clk;
this.pclk_en = 1;
this.vif.WCLK = 0;
forever begin
if (this.pclk_en == 1)begin
#50;
clk = ~clk;
this.vif.WCLK = clk;
end
else begin
`uvm_info($sformatf("%s:CLK_GEN",get_name()), "STOPPING WPCLK", UVM_LOW)
break;
end
end
endtask: wclk_gen
// ---------------------- DFI clock generation ---------------------- //
task fifo_driver::rclk_gen();
bit dficlk=0;
this.dficlk_en = 1;
this.vif.RCLK = 0;
forever begin
if (this.dficlk_en == 1)begin
#25;
dficlk = ~dficlk;
this.vif.RCLK = dficlk;
end
else begin
`uvm_info($sformatf("%s:CLK_GEN",get_name()), "STOPPING DFICLK", UVM_LOW)
break;
end
end
endtask: rclk_gen
// ---------------------- get_and_drive ---------------------- //
function fifo_driver::new(string name = "fifo_driver", uvm_component parent = null);
super.new(name, parent);
endfunction
task fifo_driver::get_and_drive();
`uvm_info($sformatf("%s:get_and_drive",get_name()), "STARTING get_and_drive", UVM_LOW)
forever begin
fifo_transaction tr;
seq_item_port.get_next_item(tr);
fork
case (tr.kind)
fifo_transaction::read : this.read( tr.rdata);
fifo_transaction::write : this.write(tr.wdata);
endcase
join_any
disable fork;
seq_item_port.item_done();
end //forever begin
`uvm_info($sformatf("%s:get_and_drive",get_name()), "STOPPING get_and_drive", UVM_LOW)
endtask: get_and_drive
// ---------------------- Read operation ---------------------- //
task fifo_driver::read(output logic [3:0] data);
this.vif.RE = 1'b1;
@(posedge this.vif.RCLK);
if (count != 1'b0) begin
data = this.vif.PRDATA;
count = count - 1;
$display("read count %d time %t",count,$time);
end
else
begin
$display("count in else part %d time %t",count,$time);
end
this.vif.RE = 1'b0;
endtask: read
//
//// ---------------------- Write operation ---------------------- //
task fifo_driver::write(input bit [3:0] data);
this.vif.WE = 1'b1;
@(posedge this.vif.WCLK);
if (count <= 20) begin
this.vif.PWDATA = data;
count = count + 1;
$display("write count %d time %t",count,$time);
//this.vif.fifo_full = 1'b0;
end
else
begin
$display("count in else part %d",count);
end
this.vif.WE = 1'b0;
endtask: write
Here I am not using Qesta sim so I won’t be able to check with this method . I will have to use scoreboard only