Regarding assert( obj.randomize() )

SystemVerilog
,
1

Hi All,
Consider the following code

class obj;
  rand bit[1:0] a;
endclass

// Within procedural code in a class / module 
obj obj_h = new(); 
assert( obj_h.randomize() );  // Immediate assertion  'assert'

Incase the randomization fails then by default $error would execute

My question is whether using assert( obj.randomize() ) have any limitations ?
Eg: If simulation were run by disabling assertions would the randomization failure go unnoticed ?

Using $assertoff( 0 , top_tb ) procedurally disable assertions in a simulation , is there a command line option as well ?

2

If the assertions are in a class declared in a package, the $assertoff( 0 , top_tb ) won’t disable assertions in packages–only those in the module top_db and the instance hierarchy below it.

Tools do have command line options to disable all assertions and unfortunately it may also prevent the expression inside the assertion from being evaluated.

3

Dave,
Since $assertoff doesn’t work with dynamic types , does SV provide any switch to disable immediate assertions from class types ?

4

SystemVerilog does not provide any tool switches. $assertoff does work with packages and other static scope. A class type is a static scope. It’s only the instance of a class that is dynamic.