Reg_model predefine reset regs value check error (quirky register?)

UVM
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2

In reply to Levard:

See Section 27.2 of the Class Reference Manual 1.2, it describes how to exclude a register or register block with:

uvm_resource_db#(bit)::set({“REG::”,regmodel.blk.get_full_name(),“.*”},“NO_REG_HW_RESET_TEST”, 1, this);