In reply to o.malnasi:
Of course it’s possible—it’s just software! I’ll have to admit most of the time I see people doing the reverse; integrating a C/C++ reference model with a UVM SystemVerilog testbench.
The question you should be asking is it practical? How much effort would it take to wrap the SystemVerilog model versus re-writing it?
It’s impossible for someone else to answer this for you without more details about the model (i.e. level of timing accuracy, independence of the reference model from the rest of the testbench). you may want to take a look at my DVCon paper: Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI.