Readmemh, hierarchical path of instance and strings

SystemVerilog
,
2

In reply to prince7273:

You can do a variation of what I describe in my Missing Link paper.

What I suggest is similar to what you do with a virtual interface, except I’m going to use an interface class.

Put this interface class definition in a package that’s actable to both your UVM component and the top-level test bench module where you setup your uvm_config_db::set()s before calling run_test. (You can also put this into an existing configuration object instead of creating a separate one.

interface class memory_abstract;
  pure virtual task readmem(string path);
endclass

Then in your test bench module, you will create a “concrete” class, an put a

module tb_top;

class memory_concrete implements memory_abstract;
  task readmem(string path);
   dut_shell.xxx.dut.u_inst1.u_inst2.u_rom.readrom({>>{path}});
  endtask
endclass

memory_concrete mc = new;

initial begin
   ...
   umm_config_db#(memory_abstract)::set(null,"","mc",mc);
   ...
   run_test();
end
...

In your testbench component:

memory_abstract ma;
task pre_reset(uvm_phase phase);
  uvm_config_db#(memory_abstract)::get(this,"","mc", ma);
  ma.readmem(mypath);