Range issue in systemverilog property

In reply to Dilip Bagadi:

Hi Dilip,
Thanks for response, but there something I don’t understand
It’s my first time to see the expression before and after the implication:
1- req_delay=delay+1’b1, this an initialization to the delay to the desired value, correct ?
So it can be req_delay = ble_tx_phy_ce_dly*(ble_div+1)

2- What follows the implication (till the CONSEQUENT) is confusing a bit, could you please clarify more or use a simpler example ?

Thank you for cooperation.