Randomize address equal to 2 to the power of values

SystemVerilog
,
7

In reply to dave_59:


class two_power_addr;
 rand bit [14:0] addr;
      bit [14:0] temp;
  constraint c_addr {temp == 3**addr;}
endclass
module tb();
  two_power_addr c;
initial
  begin
    c=new();
    for(int i=0; i<3; i++) begin      
      c.randomize();
      $display("output is %0d \n", c.addr);
    end
  end
endmodule

Hi Dave,

Is this what you are suggesting for power of 3?

I tried with Mentor Questa but it is not giving me expected output. Mostly incorrect logic.