Randomization with inline constraint

SystemVerilog
,
2

In reply to kathula venkatesh:

In base class you can write ::



   class base;
rand [1:0]var;
constraint cnt { soft var inside {2,3};}
endclass


// And override it with in-line hard constraint in class error ::

  class error;
    base b;
    b.randomize() with {var==0;} // Hard in-line Constraint takes priority !!
endclass