Randomization result with and without (solve x before y)

SystemVerilog
,
2

The way it should work is as follows:


constraint pkt_constraint1 {
    (kind==SHORT)-> (len <5);
    (kind==MED)  -> (len inside {[5:9]});
    (kind==LONG) -> (len >= 10);

The solution space is then // let S==SHORT, M == MED, L==LONG
{S,0}, {S, 1}, … {S,4} // 5 elements
{M,5}, {M, 6}, … {M, 9} // 5 elements
{L, 10}, {L, 11}, … {L, 2^31-1} // LOTS AND LOTS of elements
The solver will then randomly pick one of the sets from this set. In other words,
the probability of getting the LONG is very very high, compared to the SHORT or MED.
However, with


constraint pkt_constraint2 {
    (kind==SHORT)-> (len <5);
    (kind==MED)  -> (len inside {[5:9]});
    (kind==LONG) -> (len >= 10);
    solve kind before len;       
}

The probability of SHORT is 1/3, MED is 1/3, and LONG is 1/3.
Thus, you DO need the solve kind before len.

HOWEVER, and this is where it can get tricky, due to performance considerations, many solvers are not strictly LRM-compliant with regard to the distribution of results. The effect is that the solver will “approximate” the probability of the solution distribution for unordered variables (i.e. variables that do not participate in an explicit solve/before). That is why without the solve/before constraint it would work sort of like the solve before. You’ll need to experiment as to the statistics you would get.
However, solvers will provide LRM-compliant distribution for variables that are explicitly ordered (via solve/before constraints). Tools do provide strict LRM-compliance for the solver, even for unordered variables, by adding an option to the simulation command line (although this may reduce the performance/capacity of the solver for complex testcases).

SystemVerilog is indeed interesting! My advice for this problem, add the solve before.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
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  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
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