In reply to rgarcia07:
The motivation behind SystemVerilog’s random stability is giving testbench writers a mechanism for repeating the same sequence of random number generation (RNG) in a test while allowing for some controlled modifications to the environment for debugging and fixing the bug. That could be adding statements to aid debug as well as certain modifications to the design or testbench.
SystemVerilog facilitates this by managing the RNG seeding of $urandom, randomize(), etc. for threads and class objects. Because of backward compatibility issues with Verilog, this RNG seeding could not be applied to $random. I’ve seen cases where people freely mix $urandom and $random without understanding the ramifications. They should have marked $random for depreciation.
Another problem with $random is its seed must be manually managed, something most people never do. Then you can have the opposite problem of always generating the exact sequence of RNGs. SystemVerilog has a master RNG seeding that can easily be managed from the command line so you can easily run the same test with different RNG sequences.
This is not to say SystemVerilog has perfected random stability. It would be wise to study it further. Here’s a very good paper.