Random Generation of Address To access around the 4KB Memory Boundary inside a 4GB Memory !?!

SystemVerilog
2

In reply to desperadorocks:
Try this

class addr_rand;
   rand bit [31:0] addr;
   int delta = 5;
   int density = 1000;
   constraint c{addr % density inside {[0:delta],[density-delta:density]};}
endclass