Randc problem

SystemVerilog
5

In reply to dave_59:

Thanks. So if i understand this right, doing the following, am going to get unique values on c[0] on each iteration and unique values on c[1] for each iteration. Right?

module top;
  
class random;
  randc bit [3:0] b;
  bit [3:0] ua [3];
  randc bit [3:0] c [2];

endclass
  
  initial begin
    random r;
    r = new();
    repeat(16) begin
      assert(r.randomize());
      $display("Rand cyclic array c= %p\n",r.c);
    end


  end
  
endmodule