RAL model implication for same UVM Register with different offset (with 2 interfaces)

In reply to m_wafa:

As you have suggested, REG1 in AHB Map and SPI Map will be different as a memory location?
i.e. There will be two REG1, 1 mapped to SPI 1 mapped to AHB if we implement this way?

If yes, then 1 question:
If you think with respect to RTL, There will be always 1 register with 2 offset [As per my requirement]. In below implementation there will be 2 instances.

What is your thought on this?

// TODO: Revisit add_reg and pass the correct configuration
AHB_MAP.add_reg(REG1_INST, UVM_REG_ADDR_WIDTH'(REG1_AHB_OFFSET), “RW”, 0);
AHB_MAP.add_reg(REG2_INST, UVM_REG_ADDR_WIDTH'(REG2_AHB_OFFSET), “RW”, 0);
// …
SPI_MAP.add_reg(REG1_INST, UVM_REG_ADDR_WIDTH'(REG1_SPI_OFFSET), “RW”, 0);
SPI_MAP.add_reg(REG2_INST, UVM_REG_ADDR_WIDTH'(REG2_SPI_OFFSET), “RW”, 0);