In reply to mitesh.patel:
Hi, basically this is the flow (also driver code is below):
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reg1.write() issued
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reg2bus() done, Driver gets transaction from Sequencer
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reg1.is_busy() = 1 (this register becomes busy)
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trans starts on the bus
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trans ends on the bus, Driver calls end_tr() and item_done(), waiting for new transaction from Sequencer
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reg1.is_busy() = 0
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after some time
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new reg2.read() issued
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reg2bus() done
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reg2.is_busy() = 1 (this register becomes busy)
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Driver never gets transaction from the Sequencer
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reg2.is_busy() = 1 remains forever
virtual task run_phase(uvm_phase phase);
m_req=new();
m_req.enable_recording(“drv_item”);
void’(this.begin_tr(m_req,“sent_items”));
this.end_tr(m_req);
// Drive initial signal values to IF
…
// Call main driving task
do_access();
endtask: run_phasetask do_access();
forever begin
uvm_info(get_type_name(), $sformatf("Wait a transaction from sequencer"), UVM_LOW); seq_item_port.get_next_item(m_req);
uvm_info(get_type_name(), $sformatf(“Got a transaction from sequencer, wait mbox_full=0”), UVM_LOW);// Wait some condition while (...) @(posedge clk); `uvm_info(get_type_name(), $sformatf("Driving a transaction: %s\n", m_req.sprint()), UVM_LOW); void'(this.begin_tr(m_req,"sent_items")); // Drive signals to IF ... // Wait some small delay ... `uvm_info(get_type_name(), $sformatf("Ending a transaction"), UVM_LOW); this.end_tr(m_req); seq_item_port.item_done(); `uvm_info(get_type_name(), $sformatf("Emit item_done()"), UVM_LOW); end
endtask: do_access