Raise_objection in uvm_sequence class

In reply to chris_le:

Chris, I do not agree with you. Using objections in a sequence does not depend how you are starting the sequence. But it is really unusual to have objections in a sequence.
What I see in some projects is people are implementing objections in all places where it is legal. This ends up in a big confusion when the simulation does not stop as expected. The debug effort to find the problem is huge. The better way is to start with 1 objection mechanism in the test. If you find this does not consider all your simulation aspects you can look for an additional place.