Raise_objection in uvm_sequence class

In reply to dave_59:

In reply to chr_sue:
Actually, with no objections, your simulation will end prematurely at time 0.

Hi all, why the simulation without objections terminate at time 0 ?
In the pseudo code, i already delay 100ns , but why it terminate a time 0? Thank a lot!
here is pseudo code:

class xx extends uvm_test
function new xx
endfucntion

virtual task run_phase(uvm_phase phase);
#100ns;
`uvm_info("test","hihi",UVM_MEDIUM);
endtask

endclass