In reply to sivakrishna:
This is not correct. Race conditions happen as a result of:
- design flaws that you may or may not catch in RTL or GATE simulation by chance. Only detailed timing and/or formal analysis will catch these.
- Artifacts of simulation due to the absence of correct timing or modelling information.
Either one of these could occur in your testbench or design, and whether or not you choose to use a program block.