Race Between Assign and multiple Initial Blocks

SystemVerilog
1

module top();

wire a;
reg b;

assign a = b;

initial begin
b = 1;
end

initial begin
b = 0;
end

endmodule /

Hello @dave_59 , I am curious about to know whether assign blk is in race with the two initial blks are not. From my POV, as b is a type reg, so at the start of simulation b try to sample with X as default value of reg. So all three blks are trying to access same variable in same region at #0.

2

Yes, the three processes are in a race condition at time 0.

The values for b could have the transitions x → 0 → 1, or x → 1 → 0. The values for a could have the same transitions, or they could miss the first transition. The continuous assign statement alway sees the last transition.

3

Thanks You @dave_59