Queues in structs

SystemVerilog
,
1

Hi, I cant seem to find any references regarding this, is it possible for a struct to contain a queue inside it? Take the following basic example:

typedef struct {
  bit var1;
  int var2;
  user_defined_q var_q[$];
} user_defined_st

...
user_defined_st var_st;
user_defined_q temp;

(some assignment to temp)
...

var_st.var_q.push_back(temp);
...

Im not sure if im facing a tool issue or a systemverilog limitation, but it seems that I keep running into an error where VCS is unable to find this var_q member in the struct.

If this was not supported I would expect an error message that indicates that, however Im not seeing this. And Im sure the queue is added correctly to the struct, so its definitely there. Am I missing something obvious here?

Thanks in advance

2

With about 4 more lines, you could have had a minimal, complete reproducible example. It would also help showing the error you see.

I believe instead of

user_defined_st.var_q.push_back(temp);

you need to write

var_st.var_q.push_back(temp);
3

Apologies, hope this helps define what Im trying to accomplish:

typedef struct {
  int property1;
  int property2;
} user_defined_q

typedef struct {
  bit var1;
  int var2;
  user_defined_q var_q[$];
} user_defined_st


user_defined_st var_st;
user_defined_q temp;

temp.property1 = 10;
temp.property2 = 20;

var_st.var_q.push_back(temp);

And yes, I accidentally put the struct name instead of var_st. I have edited the original post, thanks for pointing it out.

As for the error:

Error-[MFNF] Member not found
“this.var_st.var_q”
Could not find member ‘var_q’ in structure ‘user_defined_st’

4

You still have not shown a minimal, complete reproducible example. What you show still has syntax errors, and the error message indicates there is a class involved. Here is what I mean by a minimal, complete reproducible example:

module top;
  typedef struct {
    int property1;
    int property2;
  } user_defined_q;

  typedef struct {
    bit var1;
    int var2;
    user_defined_q var_q[$];
  } user_defined_st;

  class A;
    user_defined_st var_st;
    user_defined_q temp;
    function new;
      temp.property1 = 10;
      temp.property2 = 20;
      var_st.var_q.push_back(temp);
    endfunction
  endclass
  
  A h;
  
initial begin
  h = new;
  $display("%p",h.var_st);
end
  
endmodule

This works on all tools on EDAPlayground.com

5

Hi, thanks for the example Dave. Ill keep this in mind next time.

As for my issue, the problem was that there are two places where user_defined_st is declared, once inside class A, and once in a separate package file that includes the file that contains class A.

I was trying to add the new user_defined_q variable in the package, until I came across the declaration in class A. It seems to me the issue in this case was that user_defined_st that is declared in class A, takes precedent over the declaration in the package, and so my addition to the struct declaration in the package would not have been visible to class A. Is this accurate?

6

Oh, there was a package involved in the issue. A reproducible example not only helps others see your issue, you might have discovered your issue sooner.

A wildcard package import ( import pkg::*; ) creates “candidates” for importing identifiers. The import does not actually happen unless the compiler scans the code and sees an identifier that has not been previously defined. If a later declaration with the same identifier name appears, that would be an error.