Your problem has to do with the placement of variable declarations, nothing to do with arrays. Because of the way Verilog defines the syntax for a begin/end blocks, variable declarations must come before any other statements. In your original example, eleven is declared after a function call and becomes a syntax error.
Your modified code is also illegal, but most tools just throw a warning. Best to move the variable declaration outside the initial block. See Function arguments not initializing variable inside the body