Queue of dynamic arrays

SystemVerilog
1

I am trying to create a queue of dynamic arrays. See the code below:

module tb;
  typedef int packet_item[]; // dynamic array as a data type
  packet_item packet_queue[$]; // queue of dynamic array elements
  
  initial begin
    packet_item ten = '{10,10};
    packet_queue.push_back(ten);
    packet_item eleven = '{11,11};
    packet_queue.push_back(eleven);
    foreach(packet_queue[i]) begin
      $display("Index: %0d  -- Elements: %0p",i, packet_queue[i]);
    end
  end
endmodule

This does not work at line packet_item eleven = '{11,11}; throwing a syntax error. However. if I move packet_queue.push_back(ten); after creating the array eleven, it works perfectly fine. See the modified code below:

module tb;
  typedef int packet_item[]; // dynamic array as a data type
  packet_item packet_queue[$]; // queue of dynamic array elements
  initial begin
    packet_item ten = '{10,10};
    packet_item eleven = '{11,11};
    packet_queue.push_back(ten);
    packet_queue.push_back(eleven);
    
    foreach(packet_queue[i]) begin
      $display("Index: %0d  -- Elements: %0p",i, packet_queue[i]);
    end
  end
endmodule

Can someone explain this behavior? Thank you

2

Your problem has to do with the placement of variable declarations, nothing to do with arrays. Because of the way Verilog defines the syntax for a begin/end blocks, variable declarations must come before any other statements. In your original example, eleven is declared after a function call and becomes a syntax error.

Your modified code is also illegal, but most tools just throw a warning. Best to move the variable declaration outside the initial block. See Function arguments not initializing variable inside the body