In reply to rgarcia07:
The design of the UVM is based on the old-school premise that the DUT overwhelms the testbench simulation. IMHO, not enough effort is put into analyzing and optimizing the performance of the UVM Base Class Library.
If you think your testbench going to have a performance penalty, then most likely it will. But it’s now always in the place you expect it to be. You’ll need to do some careful experiments and profiling to find out.