Questions about the usage of Pattern Matching Conditional Statements

SystemVerilog
1

Hi all,

I’m having a hard time understanding the explanation of ‘12.6 Pattern matching conditional statements’ in LRM. Are there any examples that are easier to understand?

BR

2

Pattern matching conditional statements in SV LRM 12.6 allow you to match a value against a structure-like pattern instead of only exact equality. It is mainly used with case/if to decompose packed structs or tuples.

Example:

typedef struct packed {
  logic [7:0] opcode;
  logic [3:0] addr;
} pkt_t;

pkt_t p;

if (p matches '{opcode:8'hA5, addr:'_}) begin
  // match opcode, ignore addr
end

Or with case:

case (p) inside
  '{opcode:8'hA5, addr:'_}: ...
endcase

Here '_' is a wildcard. It improves readability and avoids manual bit masking, especially for protocol decoding and structured transactions.

3

@AVAQ_Semiconductor, this is AI-generated spam. Try compiling the code first before posting.

Pattern-matching conditional statements work together with tagged unions. These features were included in a Bluespec language donation that was integrated into SystemVerilog. However, only a few simulation and synthesis tools support these features. That donation document has a few more examples, but finding more in the public domain will be hard.

4

Thanks dave