In reply to puranik.sunil@tcs.com:
You want to look at section 7.4.6 of the LRM:
module test(
input wire [31:0] udp_data_in,
output reg [7:0] data_out[3:0],
input clk,
input reset);
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
for (int i = 0; i < 4; i++) begin
data_out[i] <= 8'b0;
end
end
else begin
for (int i = 0; i < 4; i++) begin
data_out[i] <= udp_data_in[8*i + 7 -: 8];
// data_out[0] <= udp_data_in[7:0];
// data_out[1] <= udp_data_in[15:8];
// data_out[2] <= udp_data_in[23:16];
// data_out[3] <= udp_data_in[31:24];
end
end
end
endmodule