In reply to ben@SystemVerilog.us:
Hi Ben,
Do you know what region would sv force be performed in?
I was using UVM_HDL_FORCE/RELEASE and noticed an race condition between an rtl blocking statement and assertions on the same rtl signal. I think due to assertions being sampled(pre-poned) before the PLI force/release(pre-active?), which is before active region rtl assignment.
Made me curious how regular sv force worked, but couldn’t find much on it.
Thanks