Hi,
I have a question concerning use of RAL model for system-on-chip (SOC) verification. My understanding is that RAL model is used mainly for IP based verification where IP exposes one of the interfaces such as AHB, APB or AXI lite through which internal registers (for control/configuration, monitoring etc) can be accessed. For SOC based verification in which SOC uses ARM cores and high speed peripherals connected through an AXI interconnect, we do not use/cannot use RAL model but registers are accessed in simulation by writing C language test cases which would run on one of the ARM cores. The register test cases would perform read/writes of all the registers of all peripherals connected on AXI interconnect and verify if they can be read/written correctly using different patterns. These test cases would also check for Read only (RO), read/write (R/W), Write clear, read clear etc operation of the bits of all the registers. Is this understanding correct?
Our customer is expecting us to write register based sequences for register read/write test cases, which we find strange and difficult to understand.
Can someone elaborate please?
thanks and regards,
-sunil