In reply to ben@SystemVerilog.us:
sop |->write[=2] and read [=3] ##0 eop[->1]
Does This assertion will also work for " there must be three reads and two wites between SOp and EOP"?
In reply to ben@SystemVerilog.us:
sop |->write[=2] and read [=3] ##0 eop[->1]
Does This assertion will also work for " there must be three reads and two wites between SOp and EOP"?