I’m trying to understand the working of clocking blocks in detail.
I’m aware of the theory of race conditions , blocking assignments and non blocking assignments and the system Verilog event regions.
But still i couldn’t get the crux of the clocking blocks , any pointers to learn it will be helpful.
I also understand that default sample point for clocking blocks is #1step, which is really the same as sampling the data values in the Postponed region of the actual preceding time slot, because those data values will not have changed between the preceding Postponed region and the current Preponed region
Unless otherwise specified, the default input skew is 1step and the default output skew is 0.
input skew is used to sample the signal #1step before the clock edge in preponed region , output skew is used to drive the signals to DUT after the clock edge.
When we say we want to drive inputs to DUT after clock edge , are we expecting the DUT to latch this in the next clock edge?
Should the concept of clocking blocks to be understood with 2 clock edges instead of just 1 clock edge as explained in papers/internet ?
input and output here(from clocking block point of view) is in terms of TB , so if input skew is #1step and sampling is happening #1 step before the clock edge , are we not sampling a wrong value ? because we might want to see the value exactly on posedge ?
is there a way to see clocking block in action in waveforms?
Please correct my understanding if anything is wrong in above statements.
Please share any good example showing with and without clocking blocks(both for driving and sampling) and how it helps verification to avoid races.
i have one example from sunburst paper EDA Playground which shows how the output is getting driven 2ns after the clock edge.
other resources :
1 . SNUG Austin 2012 Best Paper: Taming Testbench Timing - Time's Up for Clocking Block Confusion
2 . http://www.sunburst-design.com/papers/CummingsSNUG2016AUS_VerificationTimingTesting.pdf