Question based on system verilog

In reply to cgales:

Loading work.muxtb

** Error: (vsim-3773) inter1.sv(28): Interface item ‘clk’ is not in modport ‘DUT’.

Region: /top/t2

** Error: (vsim-3043) inter1.sv(28): Unresolved reference to ‘clk’ in ob1.clk.

Region: /top/t2

** Error: (vsim-8440) inter1.sv(5): Clocking block input ob2.cb.a is not legal for the left hand side

of this or another expression.

Region: /top/t1

** Error: (vsim-8440) inter1.sv(6): Clocking block input ob2.cb.b is not legal for the left hand side

of this or another expression.

Region: /top/t1

** Error: (vsim-8440) inter1.sv(7): Clocking block input ob2.cb.sel is not legal for the left hand side

of this or another expression.

Region: /top/t1

these are the error lines shown while compiling @cgales