Question based on system verilog

SystemVerilog
,
1

hi,all
i have written a code for 2:1mux using system verilog.there is no compilation error in the code…but when i am simulating it is showing “Error loading design”.plz anyone help me to rectify my code or tell the reason why there is error loading design .below there is my code.

program muxtb(muxinfr.TEST ob2);
initial
begin
begin
ob2.cb.a={1};
ob2.cb.b={0};
ob2.cb.sel={0};
end
#5
begin
ob2.cb.a={1};
ob2.cb.b={0};
ob2.cb.sel={1};
end
#5
begin
ob2.cb.a={0};
ob2.cb.b={1};
ob2.cb.sel={1};
end
end
initial $display(“output is %d”,ob2.out_put);
endprogram

module mux_1(muxinfr.DUT ob1);
parameter s0=0;
parameter s1=1;
always@(posedge ob1.clk)
begin
case(ob1.sel)
s0:
ob1.out_put=ob1.a;
s1:
ob1.out_put=ob1.b;
default:
ob1.out_put=0;
endcase
end
endmodule

module top;
bit clk;
always #5 clk = !clk;

muxinfr ob(clk);
mux_1 t2(ob);
muxtb t1(ob);

endmodule

interface muxinfr(input bit clk);
logic a,b,sel;
logic out_put;

clocking cb@(posedge clk);
output out_put;
input a,b,sel;
endclocking

modport TEST(clocking cb,output out_put);
modport DUT(input a,input b,input sel,output out_put);
endinterface

2

Change the signal direction in clocking block
As:
clocking cb@(posedge clk);
input out_put;
output a,b,sel;//output from tb n input to dut
endclocking

3

In reply to Vivek Choudhary:

it’s showing same error…@Vivek

4

Can you post the exact error messages you get? Do the messages point to any specific line(s) of code?

5

In reply to cgales:

Loading work.muxtb

** Error: (vsim-3773) inter1.sv(28): Interface item ‘clk’ is not in modport ‘DUT’.

Region: /top/t2

** Error: (vsim-3043) inter1.sv(28): Unresolved reference to ‘clk’ in ob1.clk.

Region: /top/t2

** Error: (vsim-8440) inter1.sv(5): Clocking block input ob2.cb.a is not legal for the left hand side

of this or another expression.

Region: /top/t1

** Error: (vsim-8440) inter1.sv(6): Clocking block input ob2.cb.b is not legal for the left hand side

of this or another expression.

Region: /top/t1

** Error: (vsim-8440) inter1.sv(7): Clocking block input ob2.cb.sel is not legal for the left hand side

of this or another expression.

Region: /top/t1

these are the error lines shown while compiling @cgales

6

In reply to gowriashokan:

The error messages tell you exactly what is wrong. On line 28, the statement is:

always@(posedge ob1.clk)

The error message is:

** Error: (vsim-3773) inter1.sv(28): Interface item ‘clk’ is not in modport ‘DUT’.

ob1 is a reference to the DUT modport inside of muxinfr. The DUT modport has signals a, b, sel and out_put. There is no clk signal.

Reading and understanding the error messages can significantly help in debugging.