Question about error (Range with must be constant expression)

SystemVerilog
5

In reply to bpatel:
Array range requires constant expression. Its alternative is to use mask.


// code snippet 
bit [15:0] mask = 16'hffff ;
rand bit[3:0] lsb_indx ;

constraint c_a {
  lsb_indx inside {[0:15]}; // how many bits needs to be masked. 
  a == a  &  (mask << lsb_indx) ;
}