In reply to An Pham:
`ifndef GUARD_MONITOR_AHB_MASTER_IP
`define GUARD_MONITOR_AHB_MASTER_IP
`include "uvm_macros.svh"
import uvm_pkg::*;
//`include "SEQUENCE_ITEM_AHB_MASTER.sv"
class MONITOR_AHB_MASTER_IP extends uvm_monitor;
`uvm_component_utils(MONITOR_AHB_MASTER_IP)
//uvm_analysis_port#(SEQUENCE_ITEM_AHB_MASTER)Rcvr2Sb_port;
//uvm_analysis_port#(SEQUENCE_ITEM_AHB_MASTER)Rcvr2cover_m;
virtual INTERFACE_AHB_MASTER inf5;
//SEQUENCE_ITEM_AHB_MASTER pkt5;
function new(string name = "MONITOR_AHB_MASTER_IP",uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build_phase(uvm_phase phase);
//super.build_phase();
//Rcvr2Sb_port = new("Rcvr2Sb_port",this);
//Rcvr2cover_m = new("Rcvr2cover_m",this);
//pkt5 = SEQUENCE_ITEM_AHB_MASTER :: type_id :: create("pkt5",this);
if(!uvm_config_db#(virtual INTERFACE_AHB_MASTER)::get(this,"","inf_M",inf5))
`uvm_error("","uvm_config_db::get failed")
endfunction
covergroup ahb_m_cg @(negedge inf5.HCLK);
option.per_instance = 1;
BURST:coverpoint inf5.HBURST;
ADDR:coverpoint inf5.HADDR; //we can sample using condition using *** ADDR:coverpoint inf5.HADDR iff(condition) ***;
WDATA:coverpoint inf5.HWDATA;
SIZE:coverpoint inf5.HSIZE;
TRANS:coverpoint inf5.HTRANS{ bins idle_nonseq = (2'b00 => 2'b10);
bins nonseq[] = (2'b10 => 2'b11,2'b10,2'b00);
bins seq[] = (2'b11 => 2'b00,2'b10);
bins seq_busy_seq = (2'b11 => 2'b01 => 2'b11);
bins seq_busy_idle = (2'b11 => 2'b01 => 2'b00);}
WRITE:coverpoint inf5.HWRITE;
RESP:coverpoint inf5.HRESP{ bins okay_error = (2'b00 => 2'b01 => 2'b01);
bins okay_retry = (2'b00 => 2'b10 => 2'b10);
bins okay_split = (2'b00 => 2'b11 => 2'b11);}
READY:coverpoint inf5.HREADY{ bins resp = (1'b1 => 1'b0 => 1'b1 => 1'b1);
bins not_ready = (1'b1 => 1'b0[*2:5] => 1'b1);}
RDATA:coverpoint inf5.HRDATA;
PROT:coverpoint inf5.HPROT{ bins opcode_data = (4'bxxx0 => 4'bxxx1);
bins user_previ = (4'bxx0x => 4'bxx1x);
bins buffer_nonbuffer = (4'bx0xx => 4'bx1xx);
bins cach_noncach = (4'b0xxx => 4'b1xxx);} //IMS_AHB_M_COV_CP_PROT_0001_1
LOCK:coverpoint inf5.HLOCKx{bins lock_unlock = (1'b0 => 1'b1 => 1'b0);} //IMS_AHB_MASTER_COV_CP_LOCK_0003_1
cross BURST, ADDR, WDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_BURST_0002_2
cross BURST, ADDR, RDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_BURST_0002_2
cross SIZE, ADDR, WDATA; //IMS_AHB_MASTER_COV_CRS_SIZE_0004_2 //IMS_AHB_MASTER_COV_CRS_ADDR_0007_2 //IMS_AHB_MASTER_COV_CRS_WDATA_0008_2
cross SIZE, ADDR, RDATA; //IMS_AHB_MASTER_COV_CRS_SIZE_0004_2 //IMS_AHB_MASTER_COV_CRS_ADDR_0007_2 //IMS_AHB_SLAVE_COV_CRS_RDATA_0004_2
cross TRANS, BURST;
cross TRANS, READY; //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross TRANS, WRITE;
cross WRITE, BURST; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2
cross WRITE, TRANS; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2
cross WRITE, WDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2 //IMS_AHB_MASTER_COV_CRS_WDATA_0008_2
cross WRITE, RDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2 //IMS_AHB_SLAVE_COV_CRS_RDATA_0004_2
cross WRITE, ADDR; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2 ////IMS_AHB_MASTER_COV_CRS_ADDR_0007_2
cross WRITE, LOCK; //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2 //IMS_AHB_MASTER_COV_CRS_LOCK_0003_2
cross WRITE, READY {illegal_bins W0R0 = binsof(WRITE) intersect {0} && binsof(READY) intersect {0};} //IMS_AHB_MASTER_COV_CRS_WRITE_READ_0006_2 //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross ADDR, RESP; //IMS_AHB_MASTER_COV_CRS_ADDR_0007_2
cross WDATA, RESP, SIZE; //IMS_AHB_MASTER_COV_CRS_WDATA_0008_2
cross WDATA, READY, SIZE; //IMS_AHB_MASTER_COV_CRS_WDATA_0008_2 //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross RESP, READY; //IMS_AHB_SLAVE_COV_CRS_RESP_0001_2 //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross RESP, BURST; //IMS_AHB_SLAVE_COV_CRS_RESP_0001_2
cross RESP, TRANS; //IMS_AHB_SLAVE_COV_CRS_RESP_0001_2
cross READY, RDATA, SIZE; //IMS_AHB_SLAVE_COV_CRS_READY_0002_2 //IMS_AHB_SLAVE_COV_CRS_RDATA_0004_2
cross READY, BURST; //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross READY, ADDR; //IMS_AHB_SLAVE_COV_CRS_READY_0002_2
cross RDATA, RESP, SIZE; //IMS_AHB_SLAVE_COV_CRS_RDATA_0004_2
cross PROT, ADDR; //IMS_AHB_MASTER_COV_CRS_PROT_0001_2
cross PROT, WDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_PROT_0001_2
cross PROT, RDATA, SIZE; //IMS_AHB_MASTER_COV_CRS_PROT_0001_2
endgroup
virtual task run_phase(uvm_phase phase);
//super.run_phase();
forever
begin
@(negedge inf5.HCLK)
begin
//Rcvr2Sb_port.write(pkt5);
/*pkt5.HADDR <= inf5.HADDR;
pkt5.HWDATA <= inf5.HWDATA;
pkt5.HBURST <= inf5.HBURST;
pkt5.HSIZE <= inf5.HSIZE;
pkt5.HTRANS <= inf5.HTRANS;
pkt5.HWRITE <= inf5.HWRITE;
pkt5.HBUSREQx <= inf5.HBUSREQx;
pkt5.HPROT <= inf5.HPROT;
pkt5.HLOCKx <= inf5.HLOCKx;
Rcvr2cover_m.write(pkt5);*/
/*$display("=============================================================================");
$display("------- in Monitor Run Phase Master input side --------");
$display(" ");
$display("Add = %h -- TRANS = %b -- SIZE = %b -- BURST = %b -- WDATA = %h -- WRITE = %b -- READY = %b", inf5.HADDR, inf5.HTRANS, inf5.HSIZE, inf5.HBURST, inf5.HWDATA, inf5.HWRITE, inf5.HREADY);
$display(" ");
$display("=============================================================================");*/
if(inf5.HGRANTx && inf5.HRESETn)
ahb_m_cg.sample();
end
end
endtask
endclass
`endif
this is my code for the monitor and inside it i have mentioned covergroup but still it is not showing covergroup details in covergroup tab for particular uvm based test bench however it is showing correctly for SV based test bench.