In reply to tfitz:
Thanks for reply tfitz…
I am having one higher level sequencer(SqrH). It is connected with two lower level sequences(seqL1,seqL2). The two lower level sequences are running in different sequencer (SqrL1, SqrL2). In my case i am having only one interface (lets assume 2 i/p signals and 2 o/p signals).
Lets assume 4 sequences are running in higher sequencer. These 4 sequences will be started by one default sequence in higher sequencer(According to UVM LRM). when i am using one Lower sequencer with that higher sequencer, it is working fine. but when i introduce two lower level sequencers, both lower sequencers are trying to get sequence from higher sequencer. I thing that’s why i couldn’t get the packets in any one of the lower sequencer. Will it be solved by Virtual sequencer?
Code Snippet:
//////////////////////////////////////////////////
// Higher layer packet
//////////////////////////////////////////////////
class higher_packet extends uvm_sequence_item;
…
rand bit en_L1;
rand bit en_L2;
.....
endclass
//////////////////////////////////////////////////
// Higher layer sequence1
//////////////////////////////////////////////////
class higher_sequence1 extends uvm_sequence #(higher_packet);
…
task body();
higher_packet h_pkt, rsp_pkt;
....
start_item(h_pkt);
assert(h_pkt.randomize() with {h_pkt.en_L1 == 1;
h_pkt.en_L2 == 0; });
finish_item(h_pkt);
get_response(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Higher layer sequence2
//////////////////////////////////////////////////
class higher_sequence2 extends uvm_sequence #(higher_packet);
…
task body();
higher_packet h_pkt, rsp_pkt;
....
start_item(h_pkt);
assert(h_pkt.randomize() with {h_pkt.en_L1 == 0;
h_pkt.en_L2 == 1; });
finish_item(h_pkt);
get_response(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Higher layer sequence3
//////////////////////////////////////////////////
class higher_sequence3 extends uvm_sequence #(higher_packet);
…
task body();
higher_packet h_pkt, rsp_pkt;
....
start_item(h_pkt);
assert(h_pkt.randomize() with {h_pkt.en_L1 == 1;
h_pkt.en_L2 == 0; });
finish_item(h_pkt);
get_response(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Higher layer sequence4
//////////////////////////////////////////////////
class higher_sequence4 extends uvm_sequence #(higher_packet);
…
task body();
higher_packet h_pkt, rsp_pkt;
....
start_item(h_pkt);
assert(h_pkt.randomize() with {h_pkt.en_L1 == 0;
h_pkt.en_L2 == 1; });
finish_item(h_pkt);
get_response(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Higher layer default sequence
//////////////////////////////////////////////////
class higher_default_sequence extends uvm_sequence #(higher_packet);
/* I configured this default class in test class build phase by using set_config_string(“hsqr”, “default_sequence”, "higher_default_sequence ") and running it in top module using hsqr.start_default_sequence() */
`uvm_sequence_utils(higher_default_sequence, higher_sequencer);
.....
higher_sequence1 h_seq1;
higher_sequence2 h_seq2;
higher_sequence3 h_seq3;
higher_sequence4 h_seq4;
task body();
`uvm_do(h_seq1);
`uvm_do(h_seq2);
`uvm_do(h_seq3);
`uvm_do(h_seq4);
endtask
endclass
//////////////////////////////////////////////////
// Higher layer sequencer
//////////////////////////////////////////////////
class higher_sequencer extends uvm_sequencer #(higher_packet);
`uvm_sequencer_utils(higher_sequencer);
function new(string name = "higher_sequencer", uvm_component parent);
super.new(name, parent);
`uvm_update_sequence_lib_and_item(higher_packet) // Sequence Library Updatation (Default Sequence)
endfunction
endclass
//////////////////////////////////////////////////
// Lower layer 1 packet
//////////////////////////////////////////////////
class lower_packet1 extends uvm_sequence_item;
…
endclass
//////////////////////////////////////////////////
// Lower layer 1 sequence
//////////////////////////////////////////////////
class lower_sequence1 extends uvm_sequence #(lower_packet1);
…
uvm_sequencer #(higher_packet) hsqr;
higher_packet hpkt, rsp_pkt;
task body();
lower_packet1 lpkt1;
.....
hsqr.get(hpkt);
start_item(lpkt1);
if(hpkt.en_L1 == 1)
begin
assert(lpkt1.randomize());
.......
end
finish_item(lpkt1);
get_response(rsp);
......
hsqr.put(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Lower layer 1 sequencer
//////////////////////////////////////////////////
class lower_sequencer1 extends uvm_sequencer #(lower_packet1);
…
endclass
//////////////////////////////////////////////////
// Lower layer 2 packet
//////////////////////////////////////////////////
class lower_packet2 extends uvm_sequence_item;
…
endclass
//////////////////////////////////////////////////
// Lower layer 2 sequence
//////////////////////////////////////////////////
class lower_sequence2 extends uvm_sequence #(lower_packet2);
…
uvm_sequencer #(higher_packet) hsqr;
higher_packet hpkt, rsp_pkt;
task body();
lower_packet2 lpkt2;
.....
hsqr.get(hpkt);
start_item(lpkt2);
if(hpkt.en_L2 == 1)
begin
assert(lpkt1.randomize());
.......
end
finish_item(lpkt2);
get_response(rsp);
......
hsqr.put(rsp_pkt);
endtask
endclass
//////////////////////////////////////////////////
// Lower layer 2 sequencer
//////////////////////////////////////////////////
class lower_sequencer2 extends uvm_sequencer #(lower_packet2);
…
endclass
And finally this lower sequncer 1 will be connected to low sqr 1a , then low sqr 1a will be connected to low sqr 1b which is connected with driver. Lower level sequencer 2 will be connected with low sqr 1b.
when hseq1 or hseq3 is running it should reach the driver through the following path :
hsqr ↔ low sqr1 ↔ low sqr 1a ↔ low sqr 1b ↔ driver ↔ DUT
when hseq2 or hseq4 is running it should reach the driver through the following path :
hsqr ↔ low sqr2 ↔ low sqr 1b ↔ driver ↔ DUT
How can i achieve it? will it possible with virtual sequencer and how??
Thanks…