In reply to tfitz:
Thanks for reply tfitz. I tried your idea, making default sequence as a virtual sequence. but i am getting Fatal Error “default_seq.h_seq1 Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer”. How to solve this error?? Here default_seq is instance of higher_default_sequence in test class.
As per your idea, in virtual sequence,
class higher_default_sequence extends uvm_sequence #(higher_packet);
`uvm_object_utils(higher_default_sequence, higher_sequencer);
…
lower_sequencer1 Lsqr1;
lower_sequencer2 Lsqr2;
higher_sequence1 h_seq1;
higher_sequence2 h_seq2;
higher_sequence3 h_seq3;
higher_sequence4 h_seq4;
task body();
h_seq1.start(Lsqr1, this);
h_seq2.start(Lsqr2, this);
h_seq3.start(Lsqr1, this);
h_seq4.start(Lsqr2, this);
endtask
endclass
Here, h_seq1 will try to start in Lower sequencer 1, how it is possible?? Because h_seq1 and higher sequencer has same sequence item(h_pkt) but Lower sequencer1 or Lower sequencer2 is having different sequence item (lpkt1 or lpkt2)…I think due to this, I am getting above mentioned error. Please give some to idea to solve this bug…I am having one idea to do it, that is making two agents,
one agent will contain hsqr ↔ low sqr1 ↔ low sqr 1a ↔ low sqr 1b ↔ driver ↔ DUT
and Another agent will contain hsqr ↔ low sqr2 ↔ low sqr 1b ↔ driver ↔ DUT
Now i hope i can control higher sequences using virtual sequence in test.
Is this correct idea or any other easier way is there to do it??
Thank you.