Queries on Randomization

SystemVerilog
,
1

Hi Forum,

(1) 18.5.9 Variable ordering from SV LRM-2023 mentions

Variables may be solved in an order that is not consistent with the ordering constraints, 
provided that the outcome is the same.
An example situation where this might occur is as follows:


x == 0;
x < y;
solve y before x;

In this case, because x has only one possible assignment (0), x can be solved for before y. 
The constraint solver can use this flexibility to speed up the solving process.

(Q1) Given that all constraints are solved in parallel to form a solution space and then any of the solution is chosen, why does the LRM say that x can be solved before y ?

(2) 18.11.1 Inline constraint checker mentions

Normally, calling the randomize() method of a class that has no random variables causes the method to behave as a checker.
In other words, it assigns no random values and only returns a status: 1 if all constraints are satisfied and 0 otherwise.

For an empty class declaration

class Empty;
  // No random variables nor any constraint
endclass

Empty emp = new()
initial begin
  if( emp.randomize() ) $display(“Pass“);
end

(Q2) As there is nothing to randomize or to check (via constraint),why is randomization successful ?

Thanks in Advance

2

Solve before is a confusing keyword directive. You’re right that the final solution space remains the same regardless of the directive. The real focus is on the order in which we select values from the solution space for the random variables. I think choose or select would have been much more intuitive keywords. The LRM is just pointing out a degenerate case where the order of the selected values doesn’t matter.

Remember that a class can have constraints that can be dynamically turned on or off using the constraint_mode() method. Therefore, the complete constraint expression can be represented as 1 && active_constraint_1 && active_constraint_22 && …. If there are no active constraints, the expression simplifies to just 1, indicating a success.