Hi Moderators,
I was revisiting the topic of Randomization and examining some of its underlying concepts from a logical perspective.
I’ve listed several questions below as they all ( except for [6] ) stem from the same topic and are closely related.
[1] As per LRM "The randomize() method returns 1 if it successfully sets all the random variables and objects to valid values; otherwise, it returns 0. "
[Q] Is there a reason behind the return type of randomization being int type and not bit type ?
[2] Why does randomization failure result in long list of messages ( tool specific ) ? I couldn’t find anything regarding this in LRM.
[3] Why is randomization considered successful in absence of any constraint / random variable ?
class sample;
// No random variable / No constraint
endclass
sample s = new();
initial begin
if(s.randomize()) $display("Success");
end
[4] When would following constraint do ? Also when would it pass ?
rand Obj obj1 , obj2;
// Assume these are created before calling randomize()
constraint Handle { obj1 == obj2; }
[5] Is there a logical reason behind restricting handle types as strictly rand ? LRM mentions that declaring them as randc is illegal
[6] In SystemVerilog what is the difference between statement and expression ?
Does left-hand side and right-hand side exist in both ?
Eg1: rand_array.rsort(); // Absence of LHS.Is this a statement or expression ?
Eg2: obj = new(); // Presence of LHS.Is this a statement or expression ?
Eg3: a = b + c;// Presence of both LHS & RHS.Is this a statement or expression ?
Thanks in Advance
The SystemVerilog LRM was developed by multiple committees, with contributions from people from different backgrounds and programming languages. Achieving complete consistency across the board proved challenging. Naturally, those with a software background would tend to opt for int as the return type. Hardware verification is often perceived as a more software-centric problem.
The randomize() function’s purpose is to generate a solution that satisfies the given constraints. Without any constraints, any solution is considered valid. However, constraints must be met regardless of the presence of random variables. The constraint solver’s job is to manipulate random variable values until a solution is found that satisfies all the constraints.
As SystemVerilog is currently defined, constraints must be expressions of numeric values. Comparing object handles is not legal.
Not allowing object handles to be declared randc is simply a way to reduce the complexity of the constraint solver.
The last set of code you provided are statements, not expressions, due to the way you structured them.
Hi Dave,
What is considered as an expression ?
Is there a relation b/w a statement and expression ?
As per Section 11.2 of the SystemVerilog LRM
An expression is a construct that combines operands with operators to produce a
result that is a function of the values of the operands and the semantic meaning of the operator.
An operand can be one of the following:
..........
— Variable
..........
— A call to a user-defined function, system function, or
method that returns any of the above
int a = $urandom();
initial begin
a;
func(a); // User-defined non-void function
end
Despite the absence of operator(s), will both be considered an expression ?
Both are considered expressions, not statements. However, the formal syntax is not definitive about function calls. Only functions with void return values should be considered statements; however, most tools will give just a warning if you use a non-void function as a statement.
Thanks Dave.
Section 11.2 mentions
Any legal operand, such as a net bitselect, without any operator is considered an expression.
Hence the above two are expressions
Section 3.8 mentions
A task is called as a statement.
A void function is called as a statement.