In reply to tfitz:
Agreed - replace the instruction memory (that is outside the SPARC DUT) with a UVM agent that drives the instructions to the SPARC DUT.
Also agree on randcase for instruction generation.
NOTE: There will be many sequences of instructions that are illegal if one just lets each instructions be randomized without paying attention to instructions before and after. This is the equivalent of hangs in lab debug (very annoying) typically after a jump/branch to a bad place (ie random/bad offset) And also instruction sequences are needed to test all the pipelining corner cases. This intelligent instruction sequence generation could be done with a series of start_item/finish_item pairs in a single begin/end block in the uvm_sequence_item (the transaction)
This would be my recommendation for forwarding tests, conditional branching tests, trap detection testing, possibly many more scenarios that typically have repetitive sequneces of instructions to exercise the processor. Jumps to various addresses (ie trap and branch targets) will probably need to be recognized and provide intelligent instruction sequences at the targets or all sorts of chaos will break loose (equivalent to hangs in the lab)
Basically, tests will probably end up being a combination of directed instructions with randomized operands,
and some segments of randomized opcodes (ie segments without jumps, branches, traps (all the control transfers)
I have not looked for any papers, so i don’t know if there are any. I have just verified a lot of processors
(SPARC, MIPS, Alpha, Java, Smalltalk, Prologue…) that worked on 1st Si…
Joan Pendleton
PS Actually, thinking about it some more, the control transfers (ie jumps, branches, traps, etc) can avoid going to bad targets by NOT using the target addresses to generate next instruction, BUT INSTEAD, monitor and check the target addresses (basically the target addresses are “results” of the control transfer instructions and get checked just like other results. Then continue feeding the correct/desired instructions into the SPARC DUT. i think this would be an easier and more predictable way to test the control transfer instructions