Hi All,
We use assume some input signals in formal verification. For example, dut has three signal A,B,C.
How many assume statement do we need to constraint signal A,B,C? if the input A not have any illegal case , we don’t need to assume signal A ?
I am confused with that. Would you explain to me and give a example?
Thanks a lot!
An assume directive is a property whose condition must always hold true. The corollary to that is the condition must never be false. If you have no assume directives, no condition can be false, so every condition is available as an input.
thanks for reply.
How to know the assume statement is enough or not? for example: i can make three assume statements for input, but I can also make four assume statements for input.