In reply to ben@SystemVerilog.us:
Thank you very much for your instructive answer, Ben.
Just to to make sure that I understand you correctly, what you mean by a sanity check is applying some simple constrained random inputs to the DUT and monitor the assertions to detect unexpected behavior, right? This is what I understand from the example you gave above. The assertions are used during the sanity check so that the check goes faster and without a need for a reference model of the design. If this is the case, then the designer doesn’t need to actually compare the DUT output to some reference model’s output during the sanity check, he can be happy if no failures are reported by the assertions. Then he can deliver the code to the verification team. Please correct me if I misunderstood you.
Thanks