Prime numbers constraint

SystemVerilog
9

In reply to Bandaru sateesh:

Hi, I have run your code on eda playground platform. It’s giving some unexpected outcomes. In queue a, we are saving all prime numbers less than 200. But we didn’t mention any specific condition for the first two cases when i=0 and i=1. Due to this reason, we are getting some absurd values which are not satiating our requirement partially.
I tried to redesign the code. Please look into it. If there is any edge case, I missed out on, please mention it in this thread.

module test;
class prime_number;
  rand int a[],b[$];
  constraint abc {a.size==200; }
  constraint cba { foreach(a[i])
    a[i]==prime(i);}
 
  function int prime( int g);
    if(g <= 1)return 2;
    for(int i=2;i<g;i++)
      if(g%i==0)
          return 2; //if it is not a prime number ,returning 2 which is one of prime
      prime=g;
    endfunction
  function void post_randomize();
    a=a.unique;
   for(int i=0;i<a.size;i++)
     begin
     if(a[i]%10==7)
       b.push_back(a[i]);  //in b queue you will find prime numbers with units place as 7.
    if(b.size() == 10) break;
     end
  endfunction
endclass
 
prime_number pri;
 
initial
  begin
    pri=new;
    assert(pri.randomize);
    $display("%0p",pri.b);
  end
endmodule