Predictors

UVM
5

In reply to chr_sue:

Perhaps this example can help illustrate. The chip contains:

  1. state machine
  2. comp-A

When the chip predictor (aka the state machine) receives a “status” command, it needs to read a comp-A status register.

Available options:

  1. Chip-predictor access the comp-A predictor using a handle; read status directly.
  2. Chip-predictor access the comp-A predictor using TLM; send a “read” transaction to the predictor.
  3. Ignore the comp-A predictor; use RAL to grab the DUT register information directly from comp-A.

Option 2 doesn’t make sense, personally; the comp-A predictor already has TLM connections from the block-level agents.