“predict”, “set”, “get” are not SystemVerilog keywords; they are methods of the uvm_reg class. You have access to the UVM documentation as well as the source code to see the difference.
The uvm_reg class libraries create many different shadow copies of an actual DUT register.
Some routines are used to modify the values in those shadow copies, and others generate sequences to either modify the shadow copies, the DUT, or both.