In reply to lihan:
Not really enough information to help you.
Is the memory array in the DUT modeled as a single Verilog/SystemVerilog/VHDL memory?
How does mem_backdoor_acc access the memory?
In reply to lihan:
Not really enough information to help you.
Is the memory array in the DUT modeled as a single Verilog/SystemVerilog/VHDL memory?
How does mem_backdoor_acc access the memory?