Hi Debjit
Please add option +UVM_OBJECTION_TRACE in vsim. It is very helpful to debug.
vsim +UVM_TESTNAME=uart_sequence_test +UVM_VERBOSITY=UVM_HIGH
+UVM_OBJECTION_TRACE
-l tt.log
-f questa.tops
-sv_lib uvm_dpi
UVM_INFO ./examples/./test_lib.sv(50) @ 0: uvm_test_top [uart_sequence_test] $time
UVM_INFO ./sv/./uart_monitor.sv(127) @ 0: uvm_test_top.demo_tb0.uart0.Tx.monitor [uart_tx_monitor] Start Running
UVM_INFO ./sv/./uart_monitor.sv(127) @ 0: uvm_test_top.demo_tb0.uart0.Rx.monitor [uart_rx_monitor] Start Running
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq raised 1 objection(s) (Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=1 total=1
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx.sequencer added 1 objection(s) to its total (raised from source object , Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=0 total=1
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx added 1 objection(s) to its total (raised from source object , Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=0 total=1
And there are some codes example uses raise_objection in main_phase of test in mentor uvm cook book.
task spi_test::main_phase(uvm_phase phase);
send_spi_char_seq spi_char_seq = send_spi_char_seq::type_id::create(“spi_char_seq”);
phase.raise_objection(this, “starting spi_char_seq in main phase”);
spi_char_seq.start(m_env.m_v_sqr.apb);
#100ns;
phase.drop_objection(this, “finished send_spi_char_seq in main phase”);
endtask: main_phase
Regards,
Yao he