In reply to javatea:
By performance you mean enough resources to handle the traffic and load on the system.
A generic example would be a restaurant: can it handle the traffic and demands? Do I have enough ovens, burners, cooks, tables, waiters, etc? Also what would be the best and worst case latencies? Similar questions are asked if instead of a restaurant you are dealing with a cpu or a bus interface.
The way to handle such class of problems is to abstract the resources in terms of consume and response time, and to drive this abstracted model with demand loads that match the expected loads.
Systemverilog allows you to model the abstracted parts as it has features like queues, forked tasks, etc. SV has constraint random transactions to model the load, and coverage capabilities to gather the statistics.
I have done something like that in the past with ECSS, but SV is better. The hardest job is to model the load.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.