Passing type as an argument in functions

SystemVerilog
,
2

In reply to sasi_8985:

You can wrap your function in a parameterized virtual class.

module tb;
virtual class C#(type a); 
   static function void check;
    a s;
    $display(s);
  endfunction
 
  initial
      begin
        C#(reg)::check;
        C#(int)::check;
     end
 endmodule

This is explained in section 13.8 of the IEEE 1800-2017 LRM and some synthesis tools support this.