In reply to germanbravolopez:
First of all, I do a parameterized test to be able to test with different parameters values. Then, I pass them from cmd line to simulate after complile without need to recompile after change parameter values.
The problem is that when I send different values from cmd line the uvm_info macro does not print the new value sent from cmd line.
What can be the problem?
The problem is that parameters are constant resolved at elaboration time from the LRM:
“6.20 Constants
Constants are named data objects that never change. SystemVerilog provides three elaboration-time
constants: parameter, localparam, and specparam.”
Macros on the other hand are basically text substitution done at compile time, thus you approach of single compile multiple values for `define X AFAIK is not going to work.
I need to ask again as in the other thread, do you really need this values to be parameters instead of a bunch of values contained in a configuration class that can be passed/modified at runtime or with config_db.
HTH,
-R