Parameterizing transaction

SystemVerilog
,
1

hi all
i am writing like this in transaction.

parameter ctrl=1; 

typedef struct {
rand bit [0:((ctrl*19))]data;
} d;
class trans extends uvm_sequence_item;
`uvm_object_utils(trans)

///////////transaction variable ///////////////////
rand d link[12];

i want to control ctrl value from either test or sequence. i dnt want to parameterize my transaction using 'uvm_object_param_utils…
is there any other method to update transaction.

2

In reply to Er. Shipra:

Without knowing how you plan on using data, it is difficult to suggest other methods.

Can you make data a dynamic array?

typedef struct {
rand bit [0:19)]data[];
} d;

rand d link[12];
int ctrl; 
...
foreach (link[i]) link[i].data = new [ctrl];
3

In reply to dave_59:

In reply to Er. Shipra:
Without knowing how you plan on using data, it is difficult to suggest other methods.
Can you make data a dynamic array?

typedef struct {
rand bit [0:19)]data[];
} d;
rand d link[12];
int ctrl; 
...
foreach (link[i]) link[i].data = new [ctrl];

hi sir
no, i can not use dynamic array.
rand bit [0:19)]data… this data can be 20,40,60 or any bit set by test or configuration.