The structures in SystemVerilog can not be defined like that way. One has to define the structure separately for each vale of the parameter.
You can keep a workaround by using the macros. One needs two macros: one for every structure that is to be created and other for macro for a unique structure name. Thereafter, invoke the macros from the parameterized module/interface. This will take the overridden values from the module and create different structures accordingly. Refer to the sample code below.
`define MY_STRUCT_STAGE(NAME) \
my_struct_t_``NAME``
`define MY_STRUCT_STAGE_DEFINE(NAME, CNTR_TBL_ADDR_W, CNTR_TBL_DATA_W) \
typedef struct { \
logic [CNTR_TBL_ADDR_W-1``:0] address; \
logic [CNTR_TBL_DATA_W-1:0] data; \
} `MY_STRUCT_STAGE(NAME)
module my_module #(parameter int CNTR_TBL_ADDR_W=5, parameter int CNTR_TBL_DATA_W=6) ();
// interface my_interface #(parameter CNTR_TBL_ADDR_W=5, parameter CNTR_TBL_DATAR_W=6) ();
`MY_STRUCT_STAGE_DEFINE(stage_t, CNTR_TBL_ADDR_W, CNTR_TBL_DATA_W); // Structure with parameters CNTR_TBL_ADDR_W=7 and CNTR_TBL_DATA_W=31
`MY_STRUCT_STAGE_DEFINE(stage_t_2, CNTR_TBL_ADDR_W, CNTR_TBL_DATA_W); // Structure with different parameter values
`MY_STRUCT_STAGE(stage_t) s_0, s_1; // Structure handles
`MY_STRUCT_STAGE(stage_t_2) s_2, s_3; // Structure handles
initial begin
$display("In %m hierarchy, Width of s_0.address = %0d",$size(s_0.address));
$display("In %m hierarchy, Width of s_2.address = %0d",$size(s_2.address));
end
endmodule
//endinterface
// Top module
module top();
my_module #(9,3) m1(); // Instantiating with different width of struct variables
my_module #(1,2) m2();
endmodule
Refer to this link for some more discussion on a similar topic.