Parameterized DUT and Parameterized Interface

UVM
1

Hi All,
I have a couple of questions related to parameters in UVM.

  1. Does the concept of parameterized DUT and parameterized interface are same or different?
  2. for verifying parameterized Designs what are the approaches. Do we need to use the parameterized interface.?
  3. if i use the parameterized interface then all my UVM components are tightly coupled to the hard coded parameter? how to overcome this.
  4. what is the meaning of shared package approach in verifying the parameterized designs?

Please provide inputs.

Thanks in advance

2
  1. The concept of “parameterized” is specific to SystemVerilog. A module, interface, or class may be parameterized
  2. That’s a broad topic. You can search for parameterized testbenches as it’s a very popular topic.
  3. Try to reserve parameters for values that need to be defined at compile time (like widths of busses). There are alternatives to using virtual interfaces, such as abstract/concrete classes, that can decouple some of the parameters of the interface’s usage from the testbench.
  4. This just means the design and testbench share a package that set parameter values they import instead of trying to do parameter overrides.
3

Thanks for the answer, Dave.

Shared package is just for making all the parameters available in one centralized location so that both DUT and Tb will access it. But if we want to pull that parameterized interface, we need to go for the various approaches mentioned like abstract/concrete.

Two different issues al together

  1. maintain a Common package which will be used by both DUT and Tb.
  2. Pulling parameterized interface into the TB

Please correct me.

Thanks in advance