Parameterized Delay in Assertion

SystemVerilog
1

I want to write a simple assertion as:

property trigger_check;
  $rose(a) |-> ##{depending on CLK_CYC } $rose(b) ##1 $fell(b);
endproperty : trigger_check

Now, based on the value of CLK_CYC, the number of delay cycles should be:

  • 0 : 20 clock cycles
  • 1 : 50 clock cycles
  • 2 : 180 clock cycles
  • 3 : 290 clock cycles

Note: CLK_CYC is updated before posedge in a arrives
How can i implement this using the above assertion?

2

Using dynamic delay you could implement using a single property

Without it, one possible way would be

property trigger_check0;
  $rose(a) ##0 ( CLK_CYC == 0 ) |-> ##20 $rose(b) ##1 $fell(b);
endproperty : trigger_check0

property trigger_check1;
  $rose(a) ##0 ( CLK_CYC == 1 ) |-> ##50 $rose(b) ##1 $fell(b);
endproperty : trigger_check1
...................